Analysis of sound field distribution is a data-intense and memory-intense application. To speed up calculation, an alternative solution is to implement the analysis algorithms by FPGA. This paper presents the related issues for FPGA based sound field analysis system from the point of view of hardware implementation. Compared with other algorithms, the OCTA-FDTD algorithm consumes 49 slices in FPGA, and the system updates 536.2 million elements per second. In system architecture, the system based on the parallel architecture benefits from fast computation since the sound pressures of all elements are obtained and updated at a clock cycle. But it consumes more hardware resources, and a small sound space is simulated by a FPGA chip. In contrast, the system based on the time-sharing architecture extends the simulated sound area by expense of computation speed since the sound pressures are calculated element by element.

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