Exploring Parallelism and Energy Efficiency in a Multistage Linear-Phase Octave Filter Bank
This paper presents a high-performance and energy-aware implementation of a multistage linear-phase octave filter bank for edge system-on-chip (SoC) platforms. The algorithm relies on a cascade of stretched FIR filter stages and complementary band splitting to preserve linear phase across all outputs. While effective, mapping such structures to embedded multicore CPUs introduces significant challenges regarding state management, task synchronization, memory-traffic efficiency, and energy-aware execution. These issues are especially relevant in block-based edge-audio processing, where high throughput must be balanced against the power constraints of mobile and embedded devices. We derive a cache-friendly sequential realization using a blocked streaming schedule and compact circular state. Building on this, we propose a parallel design based on an OpenMP task pipeline with explicit dependencies to preserve the filter-bank semantics without fine-grained synchronization in the filtering tasks. Experimental results on an NVIDIA Jetson Orin Nano module show that the optimized sequential version already sustains more than 1.18 M samples/s, while the task-level pipeline reaches speedups above 4.5× for suitable block sizes. Furthermore, our analysis reveals a clear trade-off between throughput and power, showing that the most energy-efficient operating point does not necessarily coincide with maximum performance on multicore edge SoCs.